EP4SE360F35I4 Datasheet, PDF (180/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

6–6
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
Figure 6–1. Stratix IV E Devices I/0 Banks ⁽¹⁾, ⁽²⁾, ⁽³⁾, ⁽⁴⁾, ⁽⁵⁾, ⁽⁶⁾, ⁽⁷⁾, ⁽⁸⁾
Bank 8A
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
I/O banks 8A, 8B, and 8C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
I/O banks 7A, 7B, and 7C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8-V,
1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I & II,
SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15 Class I,
HSTL-12 Class I, LVDS, RSDS, mini-LVDS, differential
SSTL-2 Class I & II, differential SSTL-18 Class I & II,
differential SSTL-15 Class I, differential HSTL-18 Class I &
II, differential HSTL-15 Class I, and differential HSTL-12
Class I standards for input and output operations.
LVPECL I/O standard for input operation on dedicated
clock input pins.
SSTL-15 Class II, HSTL-15 Class II, HSTL-12 Class II,
differential SSTL-15 Class II, differential HSTL-15
Class II, differential HSTL-12 Class II standards are
only supported for input operations.
I/O banks 3A, 3B, and 3C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
I/O banks 4A, 4B, and 4C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
Bank 3A
Bank 3B
Bank 3C
Bank 4C
Bank 4B
Bank 4A
Notes to Figure 6–1:
(1) Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as
inverted.
(2) Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without differential OCT support.
(3) Column I/O supports LVDS outputs using single-ended buffers and external resistor networks.
(4) Column I/O supports PCI/PCI-X with on-chip clamp diode. Row I/O supports PCI/PCI-X with external clamp diode.
(5) Clock inputs on column I/Os are powered by V_CCCLKIN when configured as differential clock inputs. They are powered by V_CCIO when configured as
single-ended clock inputs. All outputs use the corresponding bank V_CCIO.
(6) Row I/O supports the true LVDS output buffer.
(7) Column and row I/O banks support LVPECL standards for input clock operation.
(8) Figure 6–1 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation