EP4SE360F35I4 Datasheet, PDF (135/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
5–19
Cascading PLLs
You can cascade the left/right and top/bottom PLLs through the GCLK and RCLK
networks. In addition, where two left/right or top/bottom PLLs exist next to each
other, there is a direct connection between them that does not require the GCLK or
RCLK network. Using this path reduces clock jitter when cascading PLLs.
1 Stratix IV GX devices allow cascading the left and right PLLs to transceiver PLLs
(CMU PLLs and receiver CDRs).
f For more information, refer to the “FPGA Fabric PLLs -Transceiver PLLs Cascading”
section in the Transceiver Clocking in Stratix IV Devices chapter.
When cascading PLLs in Stratix IV devices, the source (upstream) PLL must have a
low-bandwidth setting while the destination (downstream) PLL must have a
high-bandwidth setting. Ensure that there is no overlap of the bandwidth ranges of
the two PLLs.
f For more information about PLL cascading in external memory interfaces designs,
refer to the External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User
Guide.
PLLs in Stratix IV Devices
Stratix IV devices offer up to 12 PLLs that provide robust clock management and
synthesis for device clock management, external system clock management, and
high-speed I/O interfaces. The nomenclature for the PLLs follows their geographical
location in the device floor plan. The PLLs that reside on the top and bottom sides of
the device are named PLL_T1, PLL_T2, PLL_B1 and PLL_B2; the PLLs that reside on the
left and right sides of the device are named PLL_L1, PLL_L2, PLL_L3, PLL_L4, PLL_R1,
PLL_R2, PLL_R3, and PLL_R4.
Table 5–7 lists the number of PLLs available in the Stratix IV device family.
Table 5–7. PLL Availability for Stratix IV Devices (Part 1 of 2)
Device Package L1 L2 L3 L4 T1 T2 B1 B2 R1 R2 R3 R4
EP4S40G2 F1517
—
Y
Y
—
Y
Y
Y
Y
—
Y
Y
—
EP4S40G5 H1517 —
Y
Y
—
Y
Y
Y
Y
—
Y
Y
—
EP4S100G2 F1517
—
Y
Y
—
Y
Y
Y
Y
—
Y
Y
—
EP4S100G3 F1932
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EP4S100G4 F1932
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
H1517 —
Y
Y
—
Y
Y
Y
Y
—
Y
Y
—
EP4S100G5
F1932
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EP4SE230
F780
—
Y
——
Y
—
Y
——
Y
——
H780
—
Y
——
Y
—
Y
——
Y
——
EP4SE360
F1152
—
Y
Y
—
Y
Y
Y
Y
—
Y
Y
—
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1