EP4SE360F35I4 Datasheet, PDF (371/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
JTAG Configuration
10–35
f For more information about how to use the USB Blaster, MasterBlaster, ByteBlaster II,
or ByteBlasterMV cables, refer to the following user guides:
■ USB-Blaster Download Cable User Guide
■ MasterBlaster Serial/USB Communications Cable User Guide
■ ByteBlaster II Download Cable User Guide
■ ByteBlasterMV Download Cable User Guide
■ EthernetBlaster Communications Cable User Guide
JTAG Configuration
JTAG has developed a specification for boundary-scan testing. This boundary-scan
test (BST) architecture offers the capability to efficiently test components on PCBs
with tight lead spacing. The BST architecture can test pin connections without using
physical test probes and capture functional data while a device is operating normally.
You can also use JTAG circuitry to shift configuration data into the device. The
Quartus II software automatically generates .sofs that you can use for JTAG
configuration with a download cable in the Quartus II software programmer.
f For more information about JTAG boundary-scan testing and commands available
using Stratix IV devices, refer to the following documents:
■ JTAG Boundary Scan Testing in Stratix IV Devices chapter
■ Programming Support for Jam STAPL Language
Stratix IV devices are designed such that JTAG instructions have precedence over any
device configuration modes. Therefore, JTAG configuration can take place without
waiting for other configuration modes to complete. For example, if you attempt JTAG
configuration of Stratix IV devices during PS configuration, PS configuration is
terminated and JTAG configuration begins.
1 You cannot use the Stratix IV decompression or design security features if you are
configuring your Stratix IV device when using JTAG-based configuration.
1 A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK, and
one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the
TDI, TMS, and TRST pins have weak internal pull-up resistors (typically 25 k). The
JTAG output pin TDO and all JTAG input pins are powered by 2.5-V/3.0-V V_CCPD. All
the JTAG pins only support the LVTTL I/O standard.
All user I/O pins are tri-stated during JTAG configuration.
f
All the JTAG pins are powered by the V_CCPD power supply of I/O bank 1A. For more
information about how to connect a JTAG chain with multiple voltages across the
devices in the chain, refer to the JTAG Boundary Scan Testing in Stratix IV Devices
chapter.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1