EP4SE360F35I4 Datasheet, PDF (259/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–35
Table 7–8. DLL Reference Clock Input for EP4SGX70 and EP4SGX110 Devices in the 1152-Pin FineLine BGA Package
(with 24 Transceivers)
DLL
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
DLL0
DLL1
CLK12P
CLK13P
CLK14P
CLK15P
CLK4P
CLK5P
CLK6P
CLK7P
CLK0P
CLK1P
CLK2P
PLL_T1
PLL_L2
—
CLK3P
CLK0P
CLK1P
CLK2P
PLL_B1
PLL_L2
—
CLK3P
DLL2
DLL3
CLK4P
CLK5P
CLK6P
CLK7P
CLK12P
CLK13P
CLK14P
CLK15P
CLK8P
CLK9P
CLK10P
PLL_B1
PLL_R2
—
CLK11P
CLK8P
CLK9P
CLK10P
PLL_T1
PLL_R2
—
CLK11P
Table 7–9. DLL Reference Clock Input for EP4SGX110 Devices in the 1152-Pin FineLine BGA Package (with 16
Transceivers)
DLL
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
CLK12P
CLK13P
CLK0P
DLL0
PLL_T1
PLL_L2
—
CLK14P
CLK1P
CLK15P
CLK4P
CLK5P
CLK0P
DLL1
PLL_B1
—
—
CLK6P
CLK1P
CLK7P
CLK4P
CLK5P
CLK10P
DLL2
PLL_B1
—
—
CLK6P
CLK11P
CLK7P
CLK12P
CLK13P
CLK10P
DLL3
PLL_T1
PLL_R2
—
CLK14P
CLK11P
CLK15P
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1