EP4SE360F35I4 Datasheet, PDF (179/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 6: I/O Features in Stratix IV Devices
6–5
I/O Banks
Table 6–2. I/O Standards and Voltage Levels for Stratix IV Devices ⁽¹⁾ (Part 3 of 3)
I/O Standard
Standard
Support
V_CCIO (V)
Input Operation
Output Operation
Column Row
Column
Row
I/O Banks I/O Banks I/O Banks I/O Banks
V_CCPD (V)
(Pre-Driver
Voltage)
V_REF (V)
(Input Ref
Voltage)
V_TT (V)
(Board
Termination
Voltage)
LVPECL
—
(4)
2.5
—
—
2.5
—
—
Notes to Table 6–2:
(1) V_CCPD is either 2.5 or 3.0 V. For V_CCIO = 3.0 V, V_CCPD = 3.0 V. For V_CCIO = 2.5 V or less, V_CCPD = 2.5 V.
(2) Single-ended HSTL/SSTL, differential SSTL/HSTL, and LVDS input buffers are powered by V_CCPD. Row I/O banks support both true differential
input buffers and true differential output buffers. Column I/O banks support true differential input buffers, but not true differential output buffers.
I/O pins are organized in pairs to support differential standards. Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers
without on-chip R_D support.
(3) For more information about the 3.3-V LVTTL/LVCMOS standard supported in Stratix IV devices, refer to “3.3-V I/O Interface” on page 6–19.
(4) Column I/O banks support LVPECL I/O standards for input clock operation. Clock inputs on column I/Os are powered by V_CCCLKIN when configured
as differential clock inputs. They are powered by V_CCIO when configured as single-ended clock inputs. Differential clock inputs in row I/Os are
powered by V_CCPD.
(5) Column and row I/O banks support LVDS outputs using two single-ended output buffers, an external one-resistor (LVDS_E_1R), and a
three-resistor (LVDS_E_3R) network.
(6) Row I/O banks support RSDS and mini-LVDS I/O standards using a true LVDS output buffer without a resistor network.
(7) Column and row I/O banks support RSDS and mini-LVDS I/O standards using two single-ended output buffers with one-resistor (RSDS_E_1R
and mini-LVDS_E_1R) and three-resistor (RSDS_E_3R and mini-LVDS_E_3R) networks.
(8) The emulated differential output standard that supports the tri-state feature includes: LVDS_E_1R, LVDS_E_3R, RSDS_E_1R, RSDS_E_3R,
Mini_LVDS_E_1R, and Mini_LVDS_E_3R. For more information, refer to the I/O Buffer (ALTIOBUF) Megafunction User Guide.
f For more information about the electrical characteristics of each I/O standard, refer to
the DC and Switching Characteristics for Stratix IV Devices chapter.
I/O Banks
Stratix IV devices contain up to 24 I/O banks, as shown in Figure 6–1 and Figure 6–2.
The row I/O banks contain true differential input and output buffers and dedicated
circuitry to support differential standards at speeds up to 1.6 Gbps.
Each I/O bank in Stratix IV devices can support high-performance external memory
interfaces with dedicated circuitry. The I/O pins are organized in pairs to support
differential standards. Each I/O pin pair can support both differential input and
output buffers. The only exceptions are the clk[1,3,8,10], PLL_L[1,4]_clk, and
PLL_R[1,4]_clk pins, which support differential input operations only.
f
For information about the number of channels available for the LVDS I/O standard,
refer to the High-Speed Differential I/O Interface and DPA in Stratix IV Devices chapter.
For more information about transceiver-bank-related features, refer to the Transceiver
Architecture in Stratix IV Devices chapter.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1