EP4SE360F35I4 Datasheet, PDF (95/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
4–15
The second-stage and output registers are triggered by the positive edge of the clock
signal and are cleared after power up. The following DSP block signals control the
output registers within the DSP block:
■ clock[3..0]
■ ena[3..0]
■ aclr[3..0]
Stratix IV Operational Mode Descriptions
This section contains an explanation of different operational modes in Stratix IV
devices.
Independent Multiplier Modes
In independent input and output multiplier mode, the DSP block performs individual
multiplication operations for general-purpose multipliers.
9-, 12-, and 18-Bit Multiplier
You can configure each DSP block multiplier for 9-, 12-, or 18-bit multiplication. A
single DSP block can support up to eight individual 9 × 9 multipliers, six individual
12 × 12 multipliers, or four individual 18 × 18 multipliers. For operand widths up to
9 bits, a 9 × 9 multiplier is implemented. For operand widths from 10 to 12 bits, a
12 × 12 multiplier is implemented, and for operand widths from 13 to 18 bits, an
18 × 18 multiplier is implemented. This is done by the Quartus II software by
zero-padding the LSBs. Figure 4–8, Figure 4–9, and Figure 4–10 show the DSP block in
the independent multiplier operation. Table 4–9 on page 4–34 lists the dynamic
signals for the DSP block.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1