EP4SE360F35I4 Datasheet, PDF (310/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

8–30
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Stratix IV Clocking
Stratix IV Clocking
The left and right PLLs feed into the differential transmitter and receive channels
through the LVDS and DPA clock network. The center left and right PLLs can clock
the transmitter and receive channels above and below them. The corner left and right
PLLs can drive I/Os in the banks adjacent to them.
Figure 8–23 shows center PLL clocking in the Stratix IV device family. For more
information about PLL clocking restrictions, refer to “Differential Pin Placement
Guidelines” on page 8–38.
Figure 8–23. LVDS/DPA Clocks in the Stratix IV Device Family with Center PLLs
4
LVDS
Clock
DPA
Clock
4
2
Center
PLL_L2
2
Center
PLL_L3
4
LVDS DPA
4 _{Clock Clock}
Quadrant
Quadrant
Quadrant
Quadrant
DPA
Clock
LVDS
Clock
4
4
Center
PLL_R2
2
2
Center
PLL_R3
4
DPA LVDS
Clock Clock ⁴
Figure 8–24 shows center and corner PLL clocking in the Stratix IV device family. For
more information about PLL clocking restrictions, refer to “Differential Pin Placement
Guidelines” on page 8–38.
Figure 8–24. LVDS/DPA Clocks in the Stratix IV Device Family with Center and Corner PLLs
Corner
PLL_L1
2
Corner
PLL_R1
2
4 ^{LVDS DPA}
Clock Clock
Quadrant
Quadrant
DPA LVDS ₄
Clock Clock
4
2
Center
PLL_L2
2
Center
PLL_L3
4
4 ^{LVDS DPA}
Clock Clock
2
Corner
PLL_L4
Quadrant
Quadrant
4
Center ₂
PLL_R2
2
Center
PLL_R3
4
DPA LVDS ₄
Clock Clock
2
Corner
PLL_R4
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation