EP4SE360F35I4 Datasheet, PDF (141/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
5–25
Figure 5–20 shows the clock I/O pins associated with the top and bottom PLLs.
Figure 5–20. External Clock Outputs for Top and Bottom PLLs
C0
C1
C2
C3
Top/Bottom
PLLs
C4
C5
C6
C7
C8
C9
m(fbout)
clkena0 (3)
clkena1 (3)
clkena2 (3)
clkena3 (3)
clkena4 (3)
clkena5 (3)
Internal Logic
PLL_<#>_CLKOUT0p (1), (2) ^{PLL_<#>_FBp/CLKOUT1 (1), (2)}
PLL_<#>_CLKOUT3
(1), (2)
PLL_<#>_CLKOUT0n (1), (2)
PLL_<#>_FBn/CLKOUT2 (1), (2)
PLL_<#>_CLKOUT4
(1), (2)
Notes to Figure 5–20:
(1) You can feed these clock output pins using any one of the C[9..0], m counters.
(2) The CLKOUT0p and CLKOUT0n pins can be either single-ended or differential clock outputs. The CLKOUT1 and CLKOUT2 pins are
dual-purpose I/O pins that you can use as two single-ended outputs or one differential external feedback input pin. The CLKOUT3 and CLKOUT4
pins are two single-ended output pins.
(3) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1