EP4SE360F35I4 Datasheet, PDF (231/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 7: External Memory Interfaces in Stratix IV Devices
7–7
Memory Interfaces Pin Support
Table 7–2. Number of DQS/DQ Groups in Stratix IV Devices per Side (Part 3 of 3) ⁽¹⁾
Device
Package
Side
×4 ⁽²⁾
×8/×9
×16/×18 ×32/×36 ⁽³⁾ Refer to:
EP4S100G3
EP4S100G4
EP4S100G5
Left
8
1932-pin
FineLine BGA
Top/Bottom
38
Right
7
2
18
1
0
8
0
0
4
Figure 7–19
0
Notes to Table 7–2:
(1) These numbers are preliminary until the devices are available.
(2) Some of the ×4 groups may use R_UP and R_DN pins. You cannot use these groups if you use the Stratix IV calibrated OCT feature.
(3) To interface with a ×36 QDR II+/QDR II SRAM device in a Stratix IV FPGA that does not support the ×32/×36 DQS/DQ group, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(4) These ×32/×36 DQS/DQ groups have 40 pins instead of 48 pins per group. BWSn pins cannot be placed within the same DQS/DQ group as the
write data pins because of insufficient pins available.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1