EP4SE360F35I4 Datasheet, PDF (407/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

February 2011
SIV51011-3.2
SIV51011-3.2
11. SEU Mitigation in Stratix IV Devices
This chapter describes how to use the error detection cyclical redundancy check
(CRC) feature when a Stratix^® IV device is in user mode and recovers from CRC
errors. The purpose of the error detection CRC feature in the Stratix IV device is to
detect a flip in any of the configuration random access memory (CRAM) bits in
Stratix IV devices due to a soft error. With the error detection circuitry, you can
continuously verify the integrity of the configuration CRAM bits.
In critical applications such as avionics, telecommunications, system control, and
military applications, it is important to be able to do the following:
■ Confirm that the configuration data stored in a Stratix IV device is correct
■ Alert the system to the occurrence of a configuration error
1 The error detection feature is enhanced in the Stratix IV device family. Similar to
Stratix III devices, the error detection and recovery time for single-event upset (SEU)
in Stratix IV devices is reduced when compared with Stratix II devices.
f For more information about test methodology for enhanced error detection in
Stratix IV devices, refer to AN 539: Test Methodology of Error Detection and Recovery
using CRC in Altera FPGA Devices.
Dedicated circuitry is built into Stratix IV devices and consists of a CRC error
detection feature that optionally checks for SEUs continuously and automatically.
1 For Stratix IV devices, the error detection CRC feature is provided in the Quartus^® II
software version 8.0 and onwards.
Using error detection CRC for the Stratix IV device family has no impact on fitting or
performance of your device.
This chapter contains the following sections:
■ “Error Detection Fundamentals” on page 11–2
■ “Configuration Error Detection” on page 11–2
■ “User Mode Error Detection” on page 11–2
■ “Error Detection Pin Description” on page 11–5
■ “Error Detection Block” on page 11–6
■ “Error Detection Timing” on page 11–8
■ “Recovering From CRC Errors” on page 11–11
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Stratix IV Device Handbook
Volume 1
February 2011
Feedback Subscribe