EP4SE360F35I4 Datasheet, PDF (47/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
2–11
Extended LUT Mode
Use extended LUT mode to implement a specific set of seven-input functions. The set
must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four
inputs. Figure 2–9 shows the template of supported seven-input functions using
extended LUT mode. In this mode, if the seven-input function is unregistered, the
unused eighth input is available for register packing.
Functions that fit into the template shown in Figure 2–9 occur naturally in designs.
These functions often appear in designs as “if-else” statements in Verilog HDL or
VHDL code.
Figure 2–9. Template for Supported Seven-Input Functions in Extended LUT Mode
datae0
datac
dataa
datab
datad
dataf0
datae1
dataf1
(1)
5-Input
LUT
5-Input
LUT
combout0
DQ
reg0
To general or
local routing
To general or
local routing
This input is available
for register packing.
Note to Figure 2–9:
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is
not available.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1