EP4SE360F35I4 Datasheet, PDF (210/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
User Mode
In user mode, the OCTUSRCLK, ENAOCT, nCLRUSR, and ENASER[9..0] signals are used to
calibrate and serially transfer calibration codes from each OCT calibration block to
any I/O. Table 6–12 lists the user-controlled calibration block signal names and their
descriptions.
Table 6–12. OCT Calibration Block Ports for User Control
Signal Name
OCTUSRCLK
ENAOCT
ENASER[9..0]
S2PENA_<bank#>
nCLRUSR
Description
Clock for OCT block.
Enable OCT Termination (Generated by user IP).
When ENOCT = 0, each signal enables the OCT serializer for the
corresponding OCT calibration block.
When ENAOCT = 1, each signal enables OCT calibration for the
corresponding OCT calibration block.
Serial-to-parallel load enable per I/O bank.
Clear user.
Figure 6–24 shows the flow of the user signal. When ENAOCT is 1, all OCT calibration
blocks are in calibration mode; when ENAOCT is 0, all OCT calibration blocks are in
serial data transfer mode. The OCTUSRCLK clock frequency must be 20 MHz or less.
1 You must generate all user signals on the rising edge of OCTUSRCLK.
Figure 6–24 does not show transceiver banks and transceiver calibration blocks.
Figure 6–24. Signals Used for User Mode Calibration
Bank 1A
Bank 1B
CB9
CB0
CB8
ENAOCT, nCLRUSR,
CB7
CB6
Bank 6A
Bank 6B
Bank 1C
Bank 2C
Bank 2B
S2PENA_1C
Stratix IV
Core
S2PENA_6C
S2PENA_4C
OCTUSRCLK,
ENASER[N]
Bank 6C
Bank 5C
Bank 5B
CB1
Bank 2A
CB3
CB2
CB5
Bank 5A
CB4
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation