EP4SE360F35I4 Datasheet, PDF (256/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

7–32
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Figure 7–22 shows the DLL and I/O bank locations in Stratix IV devices from a
die-top view if all sides of the device support external memory interfaces.
Figure 7–22. Stratix IV DLL and I/O Bank Locations (Die-Top View)
PLL_L1
8A
8B
8C
PLL_T1 PLL_T2
7C
6
DLL0
6
1A
7B
7A
PLL_R1
6 _DLL3
6
6A
1B
6B
1C
6C
PLL_L2
PLL_L3
Stratix IV FPGA
PLL_R2
PLL_R3
2C
5C
2B
5B
2A
6
DLL1
6
PLL_L4
3A
3B
3C
PLL_B1 PLL_B2
4C
5A
6
6
DLL2
4B
4A
PLL_R4
The DLL can access the two adjacent sides from its location within the device. For
example, DLL0 on the top left of the device can access the top side (I/O banks 7A, 7B,
7C, 8A, 8B, and 8C) and the left side of the device (I/O banks 1A, 1B, 1C, 2A, 2B, and
2C). This means that each I/O bank is accessible by two DLLs, giving more flexibility
to create multiple frequencies and multiple-type interfaces. You can have two
different interfaces with the same frequency on the two sides adjacent to a DLL, where
the DLL controls the DQS delay settings for both interfaces.
Each bank can use settings from either or both DLLs the bank is adjacent to. For
example, DQS1L can get its phase-shift settings from DLL0, while DQS2L can get its
phase-shift settings from DLL1. Table 7–4 lists the DLL location and supported I/O
banks for Stratix IV devices.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation