EP4SE360F35I4 Datasheet, PDF (203/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
6–29
Expanded On-Chip Series Termination with Calibration
OCT calibration circuits always adjust OCT R_S to match the external resistors
connected to the RUP and RDN pin; however, it is possible to achieve OCT R_S values
other than the 25- and 50- resistors. Theoretically, if you need a different OCT R_S
value, you can change the resistance connected to the RUP and RDN pins accordingly.
Practically, the OCT R_S range that Stratix IV devices support is limited because of
output buffer size and granularity limitations.
The Quartus II software only allows discrete OCT R_S calibration settings of 25, 40, 50,
and 60  . You can select the closest discrete value of OCT R_S with calibration settings
in the Quartus II software to your system to achieve the closest timing. For example, if
you are using 20- OCT R_S with calibration in your system, you can select the 25-
OCT R_S with calibration setting in the Quartus II software to achieve the closest
timing.
Table 6–8 lists expanded OCT R_S with calibration supported in Stratix IV devices. Use
expanded on-chip series termination with calibration of SSTL and HSTL for
impedance matching to improve signal integrity but do not use it to meet the JEDEC
standard.
Table 6–8. Selectable I/O Standards with Expanded On-Chip Series Termination with Calibration
Range
I/O Standard
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVTTL/LVCMOS
1.2-V LVTTL/LVCMOS
SSTL-2
SSTL-18
SSTL-15
HSTL-18
HSTL-15
HSTL-12
Expanded OCT R_S Range
Row I/O ()
Column I/O ()
20–60
20–60
20–60
20–60
20–60
40–60
20–60
20–60
40–60
20–60
20–60
40–60
20–60
40–60
40–60
20–60
20–60
20–60
20–60
20–60
20–60
20–60
Dynamic On-Chip Termination
Stratix IV devices support on and off dynamic termination, both series and parallel,
for a bidirectional I/O in all I/O banks. Figure 6–21 shows the termination schemes
supported in Stratix IV devices. Dynamic parallel termination is enabled only when
the bidirectional I/O acts as a receiver and is disabled when it acts as a driver.
Similarly, dynamic series termination is enabled only when the bidirectional I/O acts
as a driver and is disabled when it acts as a receiver. This feature is useful for
terminating any high-performance bidirectional path because signal integrity is
optimized depending on the direction of the data.
Using dynamic OCT helps save power because device termination is internal instead
of external. Termination only switches on during input operation, thus drawing less
static power.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1