EP4SE360F35I4 Datasheet, PDF (100/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

4–20
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Double Multiplier
You can configure the Stratix IV DSP block to efficiently support a signed or unsigned
54 × 54-bit multiplier that is required to compute the mantissa portion of an IEEE
double-precision floating point multiplication. You can build a 54 × 54-bit multiplier
using basic 18 × 18 multipliers, shifters, and adders. In order to efficiently use the
Stratix IV DSP block’s built-in shifters and adders, a special double mode (partial
54 × 54 multiplier) is available that is a slight modification to the basic 36 × 36
multiplier mode, as shown in Figure 4–12 and Figure 4–13.
Figure 4–12. Double Mode Shown for a Half DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
dataa_0[35..18]
datab_0[35..18]
+
dataa_0[17..0]
datab_0[35..18]
dataa_0[35..18]
datab_0[17..0]
+
dataa_0[17..0]
datab_0[17..0]
Half-DSP Block
72
+
result[ ]
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation