EP4SE360F35I4 Datasheet, PDF (140/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–24
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Figure 5–19 shows a simplified block diagram of the major components of the
Stratix IV PLL.
Figure 5–19. Stratix IV PLL Block Diagram
To DPA block on
Left/Right PLLs
pfdena
Dedicated
4
clock inputs
GCLK/RCLK
Cascade input
from adjacent PLL
inclk0
Clock
inclk1
Switchover
Block
Lock
Circuit
locked
÷n
PFD
clkswitch
clkbad0
clkbad1
activeclock
CP
LF
8 ÷2
VCO
(2)
/2, /4
÷C0
8
÷C1
8
÷C2
÷C3
÷Cn ⁽¹⁾
÷m
no compensation mode
ZDB, External feedback modes
LVDS Compensation mode
Source Synchronous, normal modes
Notes to Figure 5–19:
(1) The number of post-scale counters is seven for left and right PLLs and ten for top and bottom PLLs.
(2) This is the VCO post-scale counter K.
(3) The FBOUT port is fed by the M counter in Stratix IV PLLs.
Casade output
to adjacent PLL
GCLKs
RCLKs
External clock
outputs
DIFFIOCLK from
Left/Right PLLs
LOAD_EN from
Left/Right PLLs
FBOUT (3)
External
memory
interface DLL
FBIN
DIFFIOCLK network
GCLK/RCLK network
1 You can drive the GCLK or RCLK inputs using an output from another PLL, a
pin-driven GCLK or RCLK, or through a clock control block provided the clock
control block is fed by an output from another PLL or a pin-driven dedicated GCLK
or RCLK. An internally generated global signal or general purpose I/O pin cannot
drive the PLL.
PLL Clock I/O Pins
Each top and bottom PLL supports six clock I/O pins, organized as three pairs of
pins:
■ 1st pair—two single-ended I/O or one differential I/O
■ 2nd pair—two single-ended I/O or one differential external feedback input
(FBp/FBn)
■ 3rd pair—two single-ended I/O or one differential input
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation