EP4SE360F35I4 Datasheet, PDF (316/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

8–36
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
2. Figure 8–29 shows the setting parameters for the Set Input Delay option. The
clock name must reference the source synchronous clock that feeds the LVDS
receiver. Select the desired clock using the pull-down menu.
Figure 8–29. Input Time Delay Assignment Through TimeQuest Timing Analyzer
3. Figure 8–30 shows the Targets option. You can view a list of all available ports
using the List option in the Name Finder window.
Figure 8–30. Name Finder Window in Set Input Delay Option
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation