EP4SE360F35I4 Datasheet, PDF (427/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 13: Power Management in Stratix IV Devices
Stratix IV External Power Supply Requirements
13–3
The Quartus II software sets unused device resources in the design to low-power
mode to reduce static and dynamic power. It also sets the following resources to
low-power mode when they are not used in the design:
■ LABs and MLABs
■ TriMatrix memory blocks
■ DSP blocks
If a phase-locked loop (PLL) is instantiated in the design, asserting the areset pin
high keeps the PLL in low-power mode.
Table 13–1 lists the available Stratix IV programmable power capabilities. Speed grade
considerations can add to the permutations to give you flexibility in designing your
system.
Table 13–1. Programmable Power Capabilities in Stratix IV Devices
Feature
LAB
Routing
Memory Blocks
DSP Blocks
Global Clock Networks
Programmable Power Technology
Yes
Yes
Fixed setting ⁽¹⁾
Fixed setting ⁽¹⁾
No
Note to Table 13–1:
(1) Tiles with DSP blocks and memory blocks that are used in the design are always set to high-speed mode. By
default, unused DSP blocks and memory blocks are set to low-power mode.
Stratix IV External Power Supply Requirements
This section describes the different external power supplies required to power
Stratix IV devices. You can supply some of the power supply pins with the same
external power supply, provided they have the same voltage level.
f For power supply pin connection guidelines and power regulator sharing, refer to the
Stratix IV GX and Stratix IV E Device Family Pin Connection Guidelines.
f For each Altera recommended power supply’s operating conditions, refer to the DC
and Switching Characteristics for Stratix IV Devices chapter.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1