EP4SE360F35I4 Datasheet, PDF (118/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–2
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
Table 5–1. Clock Resources in Stratix IV Devices (Part 2 of 2)
Clock Resource Number of Resources Available
Source of Clock Resource
GCLKs/RCLKs per
device
80/104 ⁽⁴⁾
16 GCLKs + 64 RCLKs
16 GCLKs + 88 RCLKs
Notes to Table 5–1:
(1) There are 64 RCLKs in the EP4S40G2, EP4S100G2, EP4SE230, EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 devices. There are 88
RCLKs in the EP4S40G5, EP4S100G3, EP4S100G4, EP4S100G5, EP4SE360, EP4SE530, EP4SE820, EP4SGX290, EP4SGX360, and
EP4SGX530 devices.
(2) There are 56 PCLKs in the EP4SGX70, and EP4SGX110 devices. There are 88 PCLKs in the EP4S40G2, EP4S100G2, EP4SE230, EP4SE360,
EP4SGX180, EP4SGX230, EP4SGX290, and EP4SGX360 devices. There are 112 PCLKs in the EP4S40G5, EP4S100G3, EP4S100G4,
EP4S100G5, EP4SE530 and EP4SGX530 devices. There are 132 PCLKs in the EP4SE820 device.
(3) There are 32 GCLKs/RCLKs per quadrant in the EP4S40G2, EP4S100G2, EP4SE230, EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230
devices. There are 38 GCLKs/RCLKs per quadrant in the EP4S40G5, EP4S100G3, EP4S100G4, EP4S100G5, EP4SE360, EP4SE530, EP4SE820,
EP4SGX290, EP4SGX360, and EP4SGX530 devices.
(4) There are 80 GCLKs/RCLKs per entire device in the EP4S40G2, EP4S100G2, EP4SE230, EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230
devices. There are 104 GCLKs/RCLKS per entire device in the EP4S40G5, EP4S100G3, EP4S100G4, EP4S100G5, EP4SE360, EP4SE530,
EP4SE820, EP4SGX290, EP4SGX360, and EP4SGX530 devices.
Stratix IV devices have up to 32 dedicated single-ended clock pins or 16 dedicated
differential clock pins (CLK[0..15]p and CLK[0..15]n) that can drive either the GCLK
or RCLK networks. These clock pins are arranged on the four sides of the Stratix IV
device, as shown in Figure 5–1 through Figure 5–4 on page 5–5.
f For more information about how to connect the clock input pins, refer to the
Stratix IV GX and Stratix IV E Device Family Pin Connection Guidelines.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation