EP4SE360F35I4 Datasheet, PDF (67/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
3–11
Figure 3–8 shows timing waveforms for read and write operations in single-port
mode with unregistered outputs. Registering the RAM’s outputs simply delays the
q output by one clock cycle.
Figure 3–8. Timing Waveform for Read-Write Operations (Single-Port Mode)
clk_a
address
rdena
wrena
bytenna
data_a
q_a (asyn)
A0
A1
01
10
00
11
A123
B456
C789
DDDD
EEEE
FFFF
A0 (old data) D_oldD_old23 B423
A1(old data) DDDD
EEEE
Simple Dual-Port Mode
All TriMatrix memory blocks support simple dual-port mode. Simple dual-port mode
allows you to perform one read and one write operation to different locations at the
same time. Write operation happens on port A; read operation happens on port B.
Figure 3–9 shows a simple dual-port configuration.
Figure 3–9. Stratix IV Simple Dual-Port Memory ⁽¹⁾
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
rdaddress[ ]
rden
q[ ]
rd_addressstall
rdclock
rdclocken
ecc_status
Note to Figure 3–9:
(1) Simple dual-port RAM supports input/output clock mode in addition to read/write clock mode.
Simple dual-port mode supports different read and write data widths (mixed-width
support). Table 3–5 lists the mixed width configurations for M9K blocks in simple
dual-port mode. MLABs do not have native support for mixed-width operation. The
Quartus II software implements mixed-width memories in MLABs by using more
than one MLAB.
Table 3–5. M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)
Read Port
Write Port
8K × 1 4K × 2 2K × 4 1K × 8 512 × 16 256 × 32 1K × 9
8K × 1
4K × 2
2K × 4
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
Y
—
Y
—
512 × 18
—
—
—
256 × 36
—
—
—
December 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1