EP4SE360F35I4 Datasheet, PDF (415/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 11: SEU Mitigation in Stratix IV Devices
Error Detection Timing
11–9
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (refer to “Software Support” on page 11–10). The divisor is a power of two,
in which n is between 1 and 8. The divisor ranges from 2 through 256. Refer to
Equation 11–1.
Equation 11–1.
error detection frequency
=
1_----0_---0_----M_------H_-----z_-
2ⁿ
1 The error detection frequency reflects the frequency of the error detection process for
a frame because the CRC calculation in the Stratix IV device is done on a per-frame
basis.
You must monitor the error message to avoid missing information in the error
message register. The error message register is updated whenever an error occurs. The
minimum interval time between each update for the error message register depends
on the device and the error detection clock frequency.
Table 11–6 lists the estimated minimum interval time between each update for the
error message register for Stratix IV devices.
Table 11–6. Minimum Update Interval for Error Message Register ⁽¹⁾
Device
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
EP4SE230
EP4SE360
EP4SE530
EP4SE820
EP4S40G2
EP4S40G5
EP4S100G2
EP4S100G3
EP4S100G4
EP4S100G5
Note to Table 11–6:
(1) These timing numbers are preliminary.
Timing Interval (s)
13.8
13.8
19.8
19.8
21.8
21.8
26.8
19.8
21.8
26.8
33.8
19.8
26.8
19.8
26.8
26.8
26.8
CRC calculation time for the error detection circuitry to check from the first until the
last frame depends on the device and the error detection clock frequency.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1