EP4SE360F35I4 Datasheet, PDF (119/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
5–3
Clock Networks in Stratix IV Devices
Global Clock Networks
Stratix IV devices provide up to 16 GCLKs that can drive throughout the device,
serving as low-skew clock sources for functional blocks such as adaptive logic
modules (ALMs), digital signal processing (DSP) blocks, TriMatrix memory blocks,
and PLLs. Stratix IV device I/O elements (IOEs) and internal logic can also drive
GCLKs to create internally generated global clocks and other high fan-out control
signals; for example, synchronous or asynchronous clears and clock enables.
Figure 5–1 shows the CLK pins and PLLs that can drive the GCLK networks in
Stratix IV devices.
Figure 5–1. GCLK Networks
CLK[12..15]
T1 T2
L1
R1
GCLK[12..15]
CLK[0..3]
L2
L3
GCLK[0..3]
GCLK[8..11]
R2
R3
CLK[8..11]
GCLK[4..7]
L4
R4
B1 B2
CLK[4..7]
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1