EP4SE360F35I4 Datasheet, PDF (194/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

6–20
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
High-Speed Differential I/O with DPA Support
Stratix IV devices have the following dedicated circuitry for high-speed differential
I/O support:
■ Differential I/O buffer
■ Transmitter serializer
■ Receiver deserializer
■ Data realignment
■ Dynamic phase aligner (DPA)
■ Synchronizer (FIFO buffer)
■ Phase-locked loops (PLLs)
f For more information about DPA support, refer to the High-Speed Differential I/O
Interfaces and DPA in Stratix IV Devices chapter.
Programmable Current Strength
The output buffer for each Stratix IV device I/O pin has a programmable current
strength control for certain I/O standards. Use programmable current strength to
mitigate the effects of high signal attenuation due to a long transmission line or a
legacy backplane. The LVTTL, LVCMOS, SSTL, and HSTL standards have several
levels of current strength that you can control. Table 6–3 lists the programmable
current strength for Stratix IV devices.
Table 6–3. Programmable Current Strength (Part 1 of 2) ⁽¹⁾, ⁽²⁾
I/O Standard
I_OH / I_OL Current Strength
Setting (mA) for
Column I/O Pins
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
16, 12, 8, 4
16, 12, 8, 4
16, 12, 8, 4
12, 10, 8, 6, 4, 2
12, 10, 8, 6, 4, 2
8, 6, 4, 2
12, 10, 8
16
12, 10, 8, 6, 4
16, 8
12, 10, 8, 6, 4
16, 8
12, 10, 8, 6, 4
16
12, 10, 8, 6, 4
16
I_OH / I_OL Current Strength
Setting (mA) for
Row I/O Pins
12, 8, 4
8, 4
12, 8, 4
8, 6, 4, 2
8, 6, 4, 2
4, 2
12, 8
16
12, 10, 8, 6, 4
16, 8
8, 6, 4
—
12, 10, 8, 6, 4
16
8, 6, 4
—
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation