EP4SE360F35I4 Datasheet, PDF (271/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–47
Figure 7–28 and Figure 7–29 show the Stratix IV write- and read-leveling circuitry.
Figure 7–28. Stratix IV Write-Leveling Delay Chains and Multiplexers ⁽¹⁾
Write clk
(-90⁰)
Write-Leveled DQS Clock
Write-Leveled DQ Clock
Note to Figure 7–28:
(1) There is one leveling delay chain per I/O sub-bank (for example, I/O sub-banks 1A, 1B, and 1C). You can only have
one memory interface in each I/O sub-bank when you use the leveling delay chain.
Figure 7–29. Stratix IV Read-Leveling Delay Chains and Multiplexers ⁽¹⁾
DQS
Resynchronization Clock
(resync_clk_2x)
delayctrlin
6
phasectrlin
4 _{phaseinvertctrl}
0111
0
1
0110
0101
0100
0011
0010
0001
0000
I/O Clock Divider (2)
use_masterin
masterin
1
DFF
0
slaveout
1
0 clkout
phaseselect
Half-Rate
Resynchronization Clock
Half-Rate Source
Synchronous Clock
Read-Leveled Resynchronization Clock
Notes to Figure 7–29:
(1) There is one leveling delay chain per I/O sub-bank (for example, I/O sub-banks 1A, 1B, and 1C). You can only have one memory interface in each
I/O sub-bank when you use the leveling delay chain.
(2) Each divider feeds up to six pins (from a 4 DQS group) in the device. To feed wider DQS groups, you must chain multiple clock dividers together
by feeding the slaveout output of one divider to the masterin input of the neighboring pins’ divider.
The –90° write clock of the ALTMEMPHY megafunction feeds the write-leveling
circuitry to produce the clock to generate the DQS and DQ signals. During
initialization, the ALTMEMPHY megafunction picks the correct write-leveled clock
for the DQS and DQ clocks for each DQS/DQ group after sweeping all the available
clocks in the write calibration process. The DQ clock output is –90° phase-shifted
compared to the DQS clock output.
Similarly, the resynchronization clock feeds the read-leveling circuitry to produce the
optimal resynchronization and postamble clock for each DQS/DQ group in the
calibration process. The resynchronization and postamble clocks can use different
clock outputs from the leveling circuitry. The output from the read-leveling circuitry
can also generate the half-rate resynchronization clock that goes to the FPGA fabric.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1