EP4SE360F35I4 Datasheet, PDF (59/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
3–3
Overview
Table 3–2 lists the capacity and distribution of the TriMatrix memory blocks in each
Stratix IV family member.
Table 3–2. TriMatrix Memory Capacity and Distribution in Stratix IV Devices
Device
EP4SE230
EP4SE360
EP4SE530
EP4SE820
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
EP4S40G2
EP4S40G5
EP4S100G2
EP4S100G3
EP4S100G4
EP4S100G5
MLABs
4,560
7,072
10,624
16,261
1,452
2,112
3,515
4,560
5,824
7,072
10,624
4,560
10,624
4,560
5,824
7,072
10,624
M9K Blocks
1,235
1,248
1,280
1,610
462
660
950
1,235
936
1,248
1,280
1,235
1280
1,235
936
1,248
1,280
M144K
Blocks
22
48
64
60
16
16
20
22
36
48
64
22
64
22
36
48
64
Total Dedicated RAM Bits
(Dedicated Memory Blocks Only)
(Kb)
14,283
18,144
20,736
23,130
6,462
8,244
11,430
14,283
13,608
18,144
20,736
14,283
20,736
14,283
13,608
18,144
20,736
Total RAM Bits
(Including MLABs)
(Kb)
17,133
22,564
27,376
33,294
7,370
9,564
13,627
17,133
17,248
22,564
27,376
17,133
27,376
17,133
17,248
22,564
27,376
TriMatrix Memory Block Types
While the M9K and M144K memory blocks are dedicated resources, the MLABs are
dual-purpose blocks. They can be configured as regular logic array blocks (LABs) or
as MLABs. Ten adaptive logic modules (ALMs) make up one MLAB. You can
configure each ALM in an MLAB as either a 64 × 1 or a 32 × 2 block, resulting in a
64 × 10 or 32 × 20 simple dual-port SRAM block in a single MLAB.
Parity Bit Support
All TriMatrix memory blocks have built-in parity-bit support. The ninth bit associated
with each byte can store a parity bit or serve as an additional data bit. No parity
function is actually performed on the ninth bit.
Byte Enable Support
All TriMatrix memory blocks support byte enables that mask the input data so that
only specific bytes of data are written. The unwritten bytes retain the previously
written values. The write enable (wren) signals, along with the byte enable (byteena)
signals, control the RAM blocks’ write operations.
December 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1