EP4SE360F35I4 Datasheet, PDF (350/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

10–14
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Fast Passive Parallel Configuration
Figure 10–5 shows the timing waveform for an FPP configuration when using a
MAX II device as an external host. This waveform shows the timing when you have
enabled the decompression and/or design security features.
Figure 10–5. FPP Configuration Timing Waveform with Decompression or Design Security Feature Enabled (Note 1), (2)
nCONFIG
t_CF2ST1
t_CFG
t_CF2CK
nSTATUS (3)
CONF_DONE (4)
DCLK
DATA[7..0]
User I/O
INIT_DONE
t_STATUS
t_CF2ST0
t_{CF2CD tST2CK}
t_CL
t_CH
12 341 234
t_CLK
Byte 0
Byte 1
t_DSU
t_DH
t_DH
High-Z
(7)
1
Byte 2
34
Byte (n-1) Byte n
(5)
(6)
User Mode
User Mode
t_CD2UM
Notes to Figure 10–5:
(1) Use this timing waveform when you have enabled the decompression and/or design security features.
(2) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
When nCONFIG is pulled low, a reconfiguration cycle begins.
(3) After power-up, the Stratix IV device holds nSTATUS low for the time of the POR delay.
(4) After power-up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) DATA[7..0] are available as user I/O pins after configuration except for some exceptions on Stratix IV GT devices. The state of these pins
depends on the dual-purpose pin settings.
(7) If needed, you can pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[7..0] pins prior to
sending the first DCLK rising edge.
Table 10–5 lists the timing parameters for Stratix IV devices for an FPP configuration
when you enable the decompression and/or the design security features.
Table 10–5. FPP Timing Parameters for Stratix IV Devices with the Decompression and/or Design Security Features
Enabled (Note 1), (2) (Part 1 of 2)
Symbol
Parameter
t_CF2CD
t_CF2ST0
t_CFG
t_STATUS
t_CF2ST1
t_CF2CK
nCONFIG low to CONF_DONE
low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS
high
nCONFIG high to first rising
edge on DCLK
Stratix IV
(7)
Minimum
Stratix IV
(8)
Maximum
Stratix IV Stratix IV Stratix IV Stratix IV
(9)
(7)
(8)
(9)
Units
—
800
ns
—
800
ns
2
—
s
10
500 (3)
s
—
500 (4)
s
500
—
s
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation