EP4SE360F35I4 Datasheet, PDF (204/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

6–30
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
1 When using calibrated input parallel and calibrated output series termination on
bidirectional pins, they must use the same termination value because each I/O pin
can only reference one OCT calibration block. The only exception is when using 50 
parallel OCT and 25  series OCT using the left shift series termination control. For
example, you cannot use calibrated 50  parallel OCT on the input buffer of a
bidirectional pin and calibrated 40  series OCT on the output buffer because these
would require two separate calibration blocks with different RUP and RDN resistor
values.
Figure 6–21. Dynamic Parallel OCT in Stratix IV Devices
Transmitter
50 Ω
VCCIO
100 Ω
100 Ω
GND
Stratix IV OCT
Z_O = 50 Ω
VCCIO
100 Ω
100 Ω
GND
Stratix IV OCT
Receiver
50 Ω
VCCIO
100 Ω
50 Ω
100 Ω
Receiver
GND
Stratix IV OCT
Z_O = 50 Ω
VCCIO
100 Ω
100 Ω
GND
50 Ω
Transmitter
Stratix IV OCT
f For more information about tolerance specifications for OCT with calibration, refer to
the DC and Switching Characteristics for Stratix IV Devices chapter.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation