EP4SE360F35I4 Datasheet, PDF (282/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

8–2
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Overview
The Stratix IV device family has the following dedicated circuitry for high-speed
differential I/O support:
■ Differential I/O buffer
■ Transmitter serializer
■ Receiver deserializer
■ Data realignment
■ DPA
■ Synchronizer (FIFO buffer)
■ Phase-locked loops (PLLs) (located on left and right sides of the device)
For high-speed differential interfaces, the Stratix IV device family supports the
following differential I/O standards:
■ LVDS
■ Mini-LVDS
■ Reduced swing differential signaling (RSDS)
In the Stratix IV device family, I/Os are divided into row and column I/Os. Figure 8–1
shows I/O bank support for the Stratix IV device family. The row I/Os provide
dedicated SERDES circuitry.
Figure 8–1. I/O Bank Support in the Stratix IV Device Family ⁽¹⁾, ⁽²⁾, ⁽³⁾, ⁽⁴⁾
LVDS I/Os
Row I/Os with
Dedicated
SERDES Circuitry (3), (4)
Column I/Os (1), (2)
LVDS Interface
with 'Use External PLL'
Option Enabled
LVDS Interface
with 'Use External PLL'
Option Disabled
Notes to Figure 8–1:
(1) Column input buffers are true LVDS buffers, but do not support 100-differential on-chip termination.
(2) Column output buffers are single ended and need external termination schemes to support LVDS, mini-LVDS, and RSDS standards. For more
information, refer to the I/O Features in Stratix IV Devices chapter.
(3) Row input buffers are true LVDS buffers and support 100-differential on-chip termination.
(4) Row output buffers are true LVDS buffers.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation