EP4SE360F35I4 Datasheet, PDF (258/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

7–34
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Table 7–6. DLL Reference Clock Input for EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA Package
DLL
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
DLL0
DLL1
DLL2
DLL3
CLK12P
CLK0P
CLK13P
CLK1P
PLL_T1
PLL_L2
—
CLK14P
CLK2P
CLK15P
CLK3P
CLK4P
CLK0P
CLK5P
CLK1P
PLL_B1
PLL_L2
—
CLK6P
CLK2P
CLK7P
CLK3P
CLK4P
CLK8P
CLK5P
CLK9P
PLL_B1
PLL_R2
—
CLK6P
CLK10P
CLK7P
CLK11P
CLK12P
CLK8P
CLK13P
CLK9P
PLL_T1
PLL_R2
—
CLK14P
CLK10P
CLK15P
CLK11P
Table 7–7. DLL Reference Clock Input for EP4SGX290 and EP4SGX360 Devices in the 780-Pin FineLine BGA Package
DLL
CLKIN (Top/Bottom)
CLKIN
(Left/Right)
PLL (Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
DLL0
DLL1
DLL2
DLL3
CLK12P
CLK13P
CLK14P
CLK15P
CLK4P
CLK5P
CLK6P
CLK7P
CLK4P
CLK5P
CLK6P
CLK7P
CLK12P
CLK13P
CLK14P
CLK15P
—
PLL_T1
—
—
—
PLL_B1
—
—
—
PLL_B2
—
—
—
PLL_T2
—
—
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation