EP4SE360F35I4 Datasheet, PDF (51/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
2–15
Similar to the carry chains, the top and bottom halves of shared arithmetic chains in
alternate LAB columns can be bypassed. This capability allows the shared arithmetic
chain to cascade through half of the ALMs in an LAB while leaving the other half
available for narrower fan-in functionality. Every other LAB column is top-half
by-passable, while the other LAB columns are bottom-half by-passable.
For more information about the shared arithmetic chain interconnect, refer to “ALM
Interconnects” on page 2–18.
LUT-Register Mode
LUT-register mode allows third-register capability within an ALM. Two internal
feedback loops allow combinational ALUT1 to implement the master latch and
combinational ALUT0 to implement the slave latch needed for the third register. The
LUT register shares its clock, clock enable, and asynchronous clear sources with the
top dedicated register. Figure 2–12 shows the register constructed using two
combinational blocks within the ALM.
Figure 2–12. LUT Register from Two Combinational Blocks
clk
aclr
4-input
LUT
sumout
combout
LUT regout
datain(datac)
sclr
5-input
LUT
sumout
combout
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1