EP4SE360F35I4 Datasheet, PDF (191/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
6–17
Figure 6–16. Number of I/Os in Each Bank in EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the 1517-Pin
FineLine BGA Package ⁽¹⁾
Number
of I/Os
Bank
Name
43 Bank 1A
22 Bank 1C
23 Bank 2C
46 Bank 2A
4 (1)
Bank
GXBL2
4 (1)
Bank
GXBL1
4 (1) ^Bank
GXBL0
EP4S40G2
EP4S40G5
EP4S100G2
EP4S100G5
Bank 6A 44
Bank 6C 23
Bank 5C 23
Bank 5A 46
Bank _{4 (1)}
GXBR2
Bank
GXBR1
4 (1)
Bank
GXBR0
4 (1)
Note to Figure 6–16:
(1) There are two additional PMA-only transceiver channels in each transceiver bank.
Bank
Name
Number
of I/Os
I/O Structure
The I/O element (IOE) in Stratix IV devices contain a bidirectional I/O buffer and I/O
registers to support a complete embedded bidirectional single data rate or DDR
transfer. The IOEs are located in I/O blocks around the periphery of the Stratix IV
device. There are up to four IOEs per row I/O block and four IOEs per column I/O
block. The row IOEs drive row, column, or direct link interconnects. The column IOEs
drive column interconnects.
The Stratix IV bidirectional IOE also supports the following features:
■ Programmable input delay
■ Programmable output-current strength
■ Programmable slew rate
■ Programmable output delay
■ Programmable bus-hold
■ Programmable pull-up resistor
■ Open-drain output
■ On-chip series termination with calibration
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1