EP4SE360F35I4 Datasheet, PDF(147/432 Page) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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EP4SE360F35I4 Datasheet, PDF (147/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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Chapter 5: Clock Networks and PLLs in Stratix IV Devices

PLLs in Stratix IV Devices

5â31

Normal Mode

An internal clock in normal mode is phase-aligned to the input clock pin. The external

clock-output pin has a phase delay relative to the clock input pin if connected in this

mode. The Quartus II software timing analyzer reports any phase difference between

the two. In normal mode, the delay introduced by the GCLK or RCLK network is fully

compensated. Figure 5â25 shows an example waveform of the PLL clocksâ phase

relationship in normal mode.

Figure 5â25. Phase Relationship Between the PLL Clocks in Normal Mode

Phase Aligned

PLL Reference

Clock at the

Input Pin

PLL Clock at the

Register Clock Port

Dedicated PLL Clock Outputs (1)

Note to Figure 5â25:

(1) The external clock output can lead or lag the PLL internal clock signals.

Zero-Delay Buffer (ZDB) Mode

In ZDB mode, the external clock output pin is phase-aligned with the clock input pin

for zero-delay through the device. When using this mode, you must use the same I/O

standard on the input clocks and output clocks to guarantee clock alignment at the

input and output pins. ZDB mode is supported on all Stratix IV PLLs.

When using Stratix IV PLLs in ZDB mode, along with single-ended I/O standards, to

ensure phase alignment between the CLK pin and the external clock output (CLKOUT)

pin, you must instantiate a bi-directional I/O pin in the design to serve as the

feedback path connecting the FBOUT and FBIN ports of the PLL. The PLL uses this

bi-directional I/O pin to mimic, and compensate for, the output delay from the clock

output port of the PLL to the external clock output pin. Figure 5â26 shows ZDB mode

in Stratix IV PLLs. When using ZDB mode, you cannot use differential I/O standards

on the PLL clock input or output pins.

1 The bi-directional I/O pin that you instantiate in your design must always be

assigned a single-ended I/O standard.

September 2012 Altera Corporation

Stratix IV Device Handbook

Volume 1

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