EP4SE360F35I4 Datasheet, PDF (281/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

September 2012
SIV51008-3.4
SIV51008-3.4
8. High-Speed Differential I/O Interfaces
and DPA in Stratix IV Devices
Overview
This chapter describes the significant advantages of the high-speed differential I/O
interfaces and the dynamic phase aligner (DPA) over single-ended I/Os and their
contribution to the overall system bandwidth achievable with Stratix^® IV FPGAs. All
references to Stratix IV devices in this chapter apply to Stratix IV E, GT, and GX
devices.
The Stratix IV device family consists of the Stratix IV E (Enhanced) devices without
high-speed clock data recovery (CDR) based transceivers, Stratix IV GT devices with
up to 48 CDR-based transceivers running up to 11.3 Gbps, and Stratix IV GX devices
with up to 48 CDR-based transceivers running up to 8.5 Gbps.
The following sections describe the Stratix IV high-speed differential I/O interfaces
and DPA:
■ “Locations of the I/O Banks” on page 8–3
■ “LVDS Channels” on page 8–4
■ “LVDS SERDES” on page 8–8
■ “ALTLVDS Port List” on page 8–9
■ “Differential Transmitter” on page 8–11
■ “Differential Receiver” on page 8–17
■ “LVDS Interface with the Use External PLL Option Enabled” on page 8–26
■ “Left and Right PLLs (PLL_Lx and PLL_Rx)” on page 8–29
■ “Stratix IV Clocking” on page 8–30
■ “Source-Synchronous Timing Budget” on page 8–31
■ “Differential Pin Placement Guidelines” on page 8–38
All Stratix IV E, GX, and GT devices have built-in serializer/deserializer (SERDES)
circuitry that supports high-speed LVDS interfaces at data rates of up to 1.6 Gbps.
SERDES circuitry is configurable to support source-synchronous communication
protocols such as Utopia, Rapid I/O, XSBI, small form factor interface (SFI), serial
peripheral interface (SPI), and asynchronous protocols such as SGMII and Gigabit
Ethernet.
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Stratix IV Device Handbook
Volume 1
September 2012
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