EP4SE360F35I4 Datasheet, PDF (23/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 1: Overview for the Stratix IV Device Family
1–9
Architecture Features
PLLs
■ Three to 12 PLLs per device supporting spread-spectrum input tracking,
programmable bandwidth, clock switchover, dynamic reconfiguration, and delay
compensation
■ On-chip PLL power supply regulators to minimize noise coupling
I/O Features
■ Sixteen to 24 modular I/O banks per device with 24 to 48 I/Os per bank designed
and packaged for optimal simultaneous switching noise (SSN) performance and
migration capability
■ Support for a wide range of industry I/O standards, including single-ended
(LVTTL/CMOS/PCI/PCIX), differential (LVDS/mini-LVDS/RSDS),
voltage-referenced single-ended and differential (SSTL/HSTL Class I/II) I/O
standards
■ On-chip series (R_S) and on-chip parallel (R_T) termination with auto-calibration for
single-ended I/Os and on-chip differential (R_D) termination for differential I/Os
■ Programmable output drive strength, slew rate control, bus hold, and weak
pull-up capability for single-ended I/Os
■ User I/O:GND:V_CC ratio of 8:1:1 to reduce loop inductance in the package—PCB
interface
■ Programmable transmitter differential output voltage (V_OD) and pre-emphasis for
high-speed LVDS I/O
High-Speed Differential I/O with DPA and Soft-CDR
■ Dedicated circuitry on the left and right sides of the device to support differential
links at data rates from 150 Mbps to 1.6 Gbps
■ Up to 98 differential SERDES in Stratix IV GX devices, up to 132 differential
SERDES in Stratix IV E devices, and up to 47 differential SERDES in Stratix IV GT
devices
■ DPA circuitry at the receiver automatically compensates for channel-to-channel
and channel-to-clock skew in source synchronous interfaces
■ Soft-CDR circuitry at the receiver allows implementation of asynchronous serial
interfaces with embedded clocks at up to 1.6 Gbps data rate (SGMII and GbE)
External Memory Interfaces
■ Support for existing and emerging memory interface standards such as DDR
SDRAM, DDR2 SDRAM, DDR3 SDRAM, QDRII SRAM, QDRII+ SRAM, and
RLDRAM II
■ DDR3 up to 1,067 Mbps/533 MHz
■ Programmable DQ group widths of 4 to 36 bits (includes parity bits)
■ Dynamic OCT, trace mismatch compensation, read-write leveling, and half-rate
register capabilities provide a robust external memory interface solution
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1