EP4SE360F35I4 Datasheet, PDF (57/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

December 2011
SIV51003-3.3
SIV51003-3.3
3. TriMatrix Embedded Memory Blocks in
Stratix IV Devices
This chapter describes the TriMatrix embedded memory blocks in Stratix^® IV devices.
TriMatrix embedded memory blocks provide three different sizes of embedded
SRAM to efficiently address the needs of Stratix IV FPGA designs. TriMatrix memory
includes 640-bit memory logic array blocks (MLABs), 9-Kbit M9K blocks, and
144-Kbit M144K blocks. MLABs have been optimized to implement filter delay lines,
small FIFO buffers, and shift registers. You can use the M9K blocks for general
purpose memory applications and the M144K blocks for processor code storage,
packet buffering, and video frame buffering.
You can independently configure each embedded memory block to be a single- or
dual-port RAM, FIFO buffer, ROM, or shift register using the Quartus^® II
MegaWizard™ Plug-In Manager. You can stitch together multiple blocks of the same
type to produce larger memories with minimal timing penalty. TriMatrix memory
provides up to 31,491 Kbits of embedded SRAM at up to 600 MHz operation.
This chapter contains the following sections:
■ “Overview”
■ “Memory Modes” on page 3–9
■ “Clocking Modes” on page 3–17
■ “Design Considerations” on page 3–18
Overview
Table 3–1 lists the features supported by the three sizes of TriMatrix memory.
Table 3–1. Summary of TriMatrix Memory Features (Part 1 of 2)
Feature
MLABs
Maximum performance
Total RAM bits
(including parity bits)
600 MHz
640
M9K Blocks
600 MHz
9216
M144K Blocks
540 MHz
147,456
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Stratix IV Device Handbook
Volume 1
December 2011
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