EP4SE360F35I4 Datasheet, PDF (319/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
8–39
You do not need a separation if a single left and right PLL is driving the DPA-enabled
channels as well as DPA-disabled channels.
Figure 8–31. Corner and Center Left and Right PLLs Driving DPA-Enabled Differential I/Os in the
Same Bank
Corner
Left /Right PLL
Reference
CLK
DPA -enabled
Diff I/O
DPA - enabled
Diff I/O
DPA - enabled
Diff I/O
DPA - enabled
Diff I/O
DPA - enabled
Diff I/O
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
Center
Left /Right PLL
Channels
driven by
Corner
Left/Right
PLL
One Unused
Channel for Buffer
Channels
driven by
Center
Left/Right
PLL
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1