EP4SE360F35I4 Datasheet, PDF (285/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
8–5
LVDS Channels
Table 8–1 and Table 8–2 list the maximum number of row and column LVDS I/Os
supported in Stratix IV E devices. You can design the LVDS I/Os as true LVDS buffers
or emulated LVDS buffers, as long as the combination of the two do not exceed the
maximum count.
For example, there are a total of 112 LVDS pairs on row I/Os in the 780-pin EP4SE230
device (refer to Table 8–1). You can design up to a maximum of 56 true LVDS input
buffers and 56 true LVDS output buffers, or up to a maximum of 112 emulated LVDS
output buffers. For the 780-pin EP4SE230 device (refer to Table 8–2), there are a total
of 128 LVDS pairs on column I/Os. You can design up to a maximum of 64 true LVDS
input buffers and 64 emulated LVDS output buffers, or up to a maximum of 128
emulated LVDS output buffers.
Table 8–1. LVDS Channels Supported in Stratix IV E Device Row I/O Banks ⁽¹⁾, ⁽²⁾, ⁽³⁾
Device
EP4SE230
EP4SE360
EP4SE530
EP4SE820
780-Pin FineLine BGA
56 Rx or eTx + 56 Tx
or eTx
56 Rx or eTx + 56 Tx
or eTx ⁽⁴⁾
—
—
1152-Pin FineLine BGA
—
88 Rx or eTx + 88 Tx
or eTx
88 Rx or eTx + 88 Tx
or eTx ⁽⁵⁾
88 Rx or eTx + 88 Tx
or eTx
1517-Pin FineLine BGA 1760- Pin FineLine BGA
—
—
—
—
112 Rx or eTx + 112 Tx
or eTx ⁽⁶⁾
112 Rx or eTx + 112 Tx
or eTx
112 Rx or eTx + 112 Tx
or eTx
132 Rx or eTx + 132 Tx
or eTx
Notes to Table 8–1:
(1) Receiver (Rx) = true LVDS input buffers with OCT R_D, Transmitter (Tx) = true LVDS output buffers, eTx = emulated LVDS output buffers (either
LVDS_E_1R or LVDS_E_3R).
(2) The LVDS Rx and Tx channels are equally divided between the left and right sides of the device.
(3) The LVDS channel count does not include dedicated clock input pins.
(4) EP4SE360 devices are offered in the H780 package instead of the F780 package.
(5) EP4SE530 devices are offered in the H1152 package instead of the F1152 package.
(6) EP4SE530 devices are offered in the H1517 package instead of the F1517 package.
Table 8–2. LVDS Channels Supported in Stratix IV E Device Column I/O Banks ⁽¹⁾, ⁽²⁾, ⁽³⁾
Device
EP4SE230
EP4SE360
780-Pin FineLine BGA
64 Rx or eTx + 64 eTx
64 Rx or eTx + 64 eTx
(4)
1152-Pin FineLine BGA
—
96 Rx or eTx + 96 eTx
1517-Pin FineLine BGA
—
—
1760-Pin FineLine BGA
—
—
EP4SE530
—
96 Rx or eTx + 96 eTx
(5)
128 Rx or eTx + 128 eTx
(6)
128 Rx or eTx + 128 eTx
EP4SE820
—
96 Rx or eTx + 96 eTx 128 Rx or eTx + 128 eTx 144 Rx or eTx + 144 eTx
Notes to Table 8–2:
(1) Rx = true LVDS input buffers without OCT R_D, eTx = emulated LVDS output buffers (either LVDS_E_1R or LVDS_E_3R).
(2) The LVDS Rx and Tx channels are equally divided between the top and bottom sides of the device.
(3) The LVDS channel count does not include dedicated clock input pins.
(4) EP4SE360 devices are offered in the H780 package instead of the F780 package.
(5) EP4SE530 devices are offered in the H1152 package instead of the F1152 package.
(6) EP4SE530 devices are offered in the H1517 package instead of the F1517 package.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1