EP2AGX95EF29C6N Datasheet, PDF (99/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
4–23
Four-Multiplier Adder
In the four-multiplier adder configuration shown in Figure 4–16, the DSP block can
implement 2 four-multiplier adders (1 four-multiplier adder per half-DSP block).
These modes are useful for implementing one-dimensional and two-dimensional
filtering applications. The four-multiplier adder is performed in two addition stages.
The outputs of two of the four multipliers are initially summed in the two first-stage
adder blocks. The results of these two adder blocks are then summed in the
second-stage adder block to produce the final four-multiplier adder result, as shown
in Equation 4–2 on page 4–4 and Equation 4–3 on page 4–5.
Figure 4–16. Four-Multiplier Adder Mode Shown for Half-DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
output_round
output_saturate
overflow (1)
dataa_0[ ]
datab_0[ ]
+
dataa_1[ ]
datab_1[ ]
dataa_2[ ]
+
result[ ]
datab_2[ ]
+
dataa_3[ ]
datab_3[ ]
Half-DSP Block
Note to Figure 4–16:
(1) Block output for accumulator overflow and saturate overflow.
Four-multiplier adder mode supports the rounding and saturation logic unit. You can
use the pipeline registers and output registers within the DSP block to pipeline the
multiplier-adder result, increasing the performance of the DSP block.
December 2010 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration