EP2AGX95EF29C6N Datasheet, PDF (23/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 1: Overview for the Arria II Device Family
1–9
Arria II Device Architecture
1 PCIe Gen2 protocol is only available in Arria II GZ devices.
The following sections provide an overview of the various features of the Arria II
FPGA.
PCIe Hard IP Block
Every Arria II device includes an integrated hard IP block which implements PCIe
PHY/MAC, data link, and transaction layers. This PCIe hard IP block is highly
configurable to meet the requirements of the majority of PCIe applications. PCIe
hard IP makes implementing PCIe Gen1 and PCIe Gen2 solution in your Arria II
design simple and easy.
You can instantiate PCIe hard IP block using the PCI Compiler MegaWizard^TM
Plug-In Manager, similar to soft IP functions, but does not consume core FPGA
resources or require placement, routing, and timing analysis to ensure correct
operation of the core. Table 1–6 lists the PCIe hard IP block support for Arria II GX
and GZ devices.
Table 1–6. PCIe Hard IP Block Support
Support
PCIe Gen1
PCIe Gen2
Root Port and endpoint configurations
Payloads
Arria II GX Devices
x1, x4, x8
—
Yes
128-byte to 256-byte
Arria II GZ Devices
x1, x4, x8
x1, x4
Yes
128-byte to 2K-byte
Logic Array Block and Adaptive Logic Modules
■ Logic array blocks (LABs) consists of 10 ALMs, carry chains, shared arithmetic
chains, LAB control signals, local interconnect, and register chain connection lines
■ ALMs expand the traditional four-input LUT architecture to eight-inputs,
increasing performance by reducing logic elements (LEs), logic levels, and
associated routing
■ LABs have a derivative called MLAB, which adds SRAM-memory capability to
the LAB
■ MLAB and LAB blocks always coexist as pairs, allowing up to 50% of the logic
(LABs) to be traded for memory (MLABs)
Embedded Memory Blocks
■ MLABs, M9K, and M144K embedded memory blocks provide up to 20,836 Kbits
of on-chip memory capable of up to 540-MHz performance. The embedded
memory structure consists of columns of embedded memory blocks that you can
configure as RAM, FIFO buffers, and ROM.
■ Optimized for applications such as high-throughput packet processing,
high-definition (HD) line buffers for video processing functions, and embedded
processor program and data storage.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration