EP2AGX95EF29C6N Datasheet, PDF (313/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
PS Configuration
9–27
The Arria II device receives configuration data on the DATA0 pin and the clock is
received on the DCLK pin. Data is latched into the device on the rising edge of DCLK. If
you are using configuration data in .rbf, .hex, or .ttf format, you must send the LSB of
each data byte first. For example, if the .rbf contains the byte sequence
02 1B EE 01 FA, the serial bitstream you must transmit to the device is
0100-0000 1101-1000 0111-0111 1000-0000 0101-1111.
Figure 9–11 shows how to configure multiple devices using an external host. This
circuit is similar to the PS configuration circuit for a single device, except the Arria II
devices are cascaded for multi-device configuration.
Figure 9–11. Multi-Device PS Configuration Using an External Host
Memory
ADDR DATA[0]
External Host
(MAX II Device or
Microprocessor)
(1) (1) (2)
10 kΩ
10 kΩ 10 kΩ
GND
Arria II Device 1
MSEL[n..0]
CONF_DONE
nSTATUS
nCE
nCEO
(1)
(3)
10 kΩ
DATA[0]
nCONFIG
DCLK
Arria II Device 2
MSEL[n..0]
CONF_DONE
nSTATUS
nCE
nCEO
(3)
N.C.
DATA[0]
nCONFIG
DCLK
Notes to Figure 9–11:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the Arria II device. For Arria II GX devices, use the V_CCIO pin.
For Arria II GZ devices, use the V_CCPGM pin. V_CCIO/V_CCPGM must be high enough to meet the V_IH specification of the I/O on both the device and the
external host. Altera recommends powering up the configuration system I/Os with V_CCIO/V_CCPGM.
(2) A pull-up resistor to V_CCIO/V_CCPGM or a pull-down resistor keeps the nCONFIG line in a known state when the external host is not driving the line.
(3) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0]for an Arria II GX device, refer to
Table 9–6 on page 9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to Table 9–7 on page 9–10.
In Arria II devices, the initialization clock source is either the internal oscillator or the
optional CLKUSR pin. By default, the internal oscillator is the clock source for
initialization. If you use the internal oscillator, the Arria II device provides itself with
enough clock cycles for proper initialization. Therefore, if the internal oscillator is the
initialization clock source, sending the entire configuration file to the device is
sufficient to configure and initialize the device. Driving DCLK to the device after
configuration is complete does not affect device operation.
You also have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. You can turn on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II software from the
General tab of the Device and Pin Options dialog box. If you supply a clock on
CLKUSR, it does not affect the configuration process. Arria II devices support f_MAX of
125 MHz.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration