EP2AGX95EF29C6N Datasheet, PDF (21/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 1: Overview for the Arria II Device Family
1–7
Arria II Device Architecture
Figure 1–2. Architecture Overview for Arria II GZ Device
General Purpose
I/O and Memory
Interface
PLL PLL
General Purpose
I/O and Memory
Interface
PLL (1)
PLL (2)
Arria II GZ FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
PLL (1)
PLL (2)
General Purpose
I/O and Memory
Interface
PLL PLL
General Purpose
I/O and Memory
Interface
Transceiver Block
400 Mbps-6.375 Gbps CDR-based Transceiver
General Purpose I/O and
High-Speed LVDS I/O
with DPA and Soft CDR
General Purpose I/O and 150 Mbps-1.25 Gbps
LVDS interface with DPA and Soft-CDR
Notes to Figure 1–2:
(1) Not available for 780-pin FBGA package.
(2) Not available for 780-pin and 1152-pin FBGA packages.
(3) The PCIe hard IP block is located on the left side of the device only (IOBANK_QL).
High-Speed Transceiver Features
Arria II GX devices integrate up to 16 transceivers and Arria II GZ devices up to
24 transceivers on a single device. The transceiver block is optimized for cost and
power consumption. Arria II transceivers support the following features:
■ Configurable pre-emphasis and equalization, and adjustable output differential
voltage
■ Flexible and easy-to-configure transceiver datapath to implement proprietary
protocols
■ Signal integrity features
■ Programmable transmitter pre-emphasis to compensate for inter-symbol
interference (ISI)
■ User-controlled receiver equalization with up to 7 dB (Arria II GX) and
16 dB (Arria II GZ) of high-frequency gain
■ On-die power supply regulators for transmitter and receiver PLL charge pump
and voltage-controlled oscillator (VCO) for superior noise immunity
■ Calibration circuitry for transmitter and receiver on-chip termination (OCT)
resistors
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration