EP2AGX95EF29C6N Datasheet, PDF (296/380 Pages) Altera Corporation – Device Interfaces and Integration

9–10
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Configuration Schemes
Table 9–6. Configuration Schemes for Arria II GX Devices (Part 2 of 2)
Configuration Scheme
MSEL3
MSEL2
MSEL1
MSEL0
Configuration
POR Delay
Voltage
Standard (V) (1)
0
0
1
1
Fast
3.3
1
1
0
1
Fast
3.0, 2.5
AS with or without remote system upgrade
1
1
1
0
Standard
3.3
1
1
1
1
Standard
3.0, 2.5
JTAG-based configuration (3)
(4)
(4)
(4)
(4)
—
—
Notes to Table 9–6:
(1) Configuration voltage standard applied to the V_CCIO power supply in which the configuration pins reside.
(2) These modes are only supported when using a MAX II device or a microprocessor with flash memory for configuration. In these modes, the
host system must output a DCLK that is x4 the data rate.
(3) JTAG-based configuration takes precedence over other configuration schemes, which means the MSEL pin settings are ignored. JTAG-based
configuration does not support the design security or decompression features.
(4) Do not leave the MSEL pins floating. Connect them to V_CCPD or GND. These pins support the non-JTAG configuration scheme used in production.
If you only use the JTAG configuration, Altera recommends connecting the MSEL pins to GND.
Table 9–7 lists the configuration schemes for Arria II GZ devices.
Table 9–7. Configuration Schemes for Arria II GZ Devices
Configuration Scheme
MSEL2 MSEL1 MSEL0
POR Delay
Configuration
Voltage
Standard (V)
FPP
0
0
0
Fast/Standard 3.0, 2.5, 1.8
PS
0
1
0
Fast/Standard 3.0, 2.5, 1.8
Fast AS (40 MHz) (1)
0
1
1
Fast/Standard 3.0, 2.5, 1.8
Remote system upgrade fast AS (40 MHz) (1)
0
1
1
Fast/Standard 3.0, 2.5, 1.8
FPP with design security feature and/or
decompression enabled (2)
0
0
1
Fast/Standard 3.0, 2.5, 1.8
JTAG-based configuration (3)
(4)
(4)
(4)
—
—
Notes to Table 9–7:
(1) Arria II GZ devices only support fast AS configuration. You must use either EPCS64 or EPCS128 devices to configure an Arria II GZ device in
fast AS mode.
(2) These modes are only supported when using a MAX II device or microprocessor with flash memory for configuration. In these modes, the host
system must output a DCLK that is x4 the data rate.
(3) The JTAG-based configuration takes precedence over other configuration schemes, which means the MSEL pin settings are ignored. The
JTAG-based configuration does not support the design security or decompression features.
(4) Do not leave the MSEL pins floating, connect them to V_CCPGM or GND. These pins support non-JTAG configuration scheme used in production.
If you only use the JTAG configuration, Altera recommends connecting the MSEL pins to GND.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation