EP2AGX95EF29C6N Datasheet, PDF (120/380 Pages) Altera Corporation – Device Interfaces and Integration

5–12
Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Table 5–3. Clock Input Pin Connectivity to the GCLK Networks for Arria II GZ Devices (Part 2 of 2)
Clock Resources
GCLK[8..11]
GCLK[12..15]
CLK (p/n Pins)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
— — — — — — — — v v v v— — — —
— ——— —— —— —— —— vvvv
Table 5–4 and Table 5–5 list the connectivity between the dedicated clock input pins
and RCLKs in Arria II devices. A given clock input pin can drive two adjacent RCLK
networks to create a dual-RCLK network.
Table 5–4. Clock Input Pin Connectivity to RCLK Networks for Arria II GX Devices
Clock Resource
RCLK [12, 14, 16, 18, 20, 22]
RCLK [13, 15, 17, 19, 21, 23]
RCLK [24..35]
RCLK [36, 38, 40, 42, 44, 46]
RCLK [37, 39, 41, 43, 45, 47]
CLK (p/n Pins)
4 5 6 7 8 9 10 11 12 13 14 15
v— v— — — — — — ———
— v— v— — — — — ———
— — — — v v v v— ———
— — — — — — — — v—v—
— — — — — — — — — v— v
Table 5–5. Clock Input Pin Connectivity to the RCLK Networks for Arria II GZ Devices (Part 1 of 2)
Clock Resource
RCLK [0, 4, 6, 10]
CLK (p/n Pins)
0 1 2 3 4 5 6 7 8 9 10 11 12
v— — — — — — — — — — — —
13 14 15
———
RCLK [1, 5, 7, 11]
— _v — — — — — — — — — — — ———
RCLK [2, 8]
— — _v — — — — — — — — — — ———
RCLK [3, 9]
— — — _v — — — — — — — — — ———
RCLK [13, 17, 21, 23, _{— — — — v — — — — — — — — — — —}
27, 31]
RCLK [12, 16, 20, 22, _{— — — — — v — — — — — — — — — —}
26, 30]
RCLK [15, 19, 25, 29] — — — — — — v — — — — — — — — —
RCLK [14, 18, 24, 28] — — — — — — — v — — — — — — — —
RCLK [35, 41]
— — — — — — — — v — — — — ———
RCLK [34, 40]
— — — — — — — — — v — — — ———
RCLK [33, 37, 39, 43] — — — — — — — — — — v — — — — —
RCLK [32, 36, 38, 42] — — — — — — — — — — — v — — — —
RCLK [47, 51, 57, 61] — — — — — — — — — — — — v — — —
RCLK [46, 50, 56, 60] — — — — — — — — — — — — — v — —
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation