EP2AGX95EF29C6N Datasheet, PDF (52/380 Pages) Altera Corporation – Device Interfaces and Integration

3–4
Chapter 3: Memory Blocks in Arria II Devices
Memory Features
The default value for the byte enable signals is high (enabled), in which case writing is
controlled only by the write enable signals. The byte enable registers have no clear
port. When using parity bits on the M9K and M144K blocks, the byte enable controls
all 9 bits (8 bits of data plus 1 parity bit). When using parity bits on the MLAB, the
byte-enable controls all 10 bits in the widest mode.
Byte enables are only supported for true dual-port memory configurations when both
the PortA and PortB data widths of the individual M9K memory blocks are multiples
of 8 or 9 bits. For example, you cannot use byte enable for a mixed data width
memory configured with portA=32 and portB=8 because the mixed data width
memory is implemented as 2 separate 16 x 4 bit memories.
Byte enables operate in a one-hot fashion, with the LSB of the byteena signal
corresponding to the LSB of the data bus. For example, if you use a RAM block in ×18
mode, byteena = 01, data[8..0] is enabled and data[17..9] is disabled. Similarly, if
byteena = 11, both data[8..0] and data[17..9] are enabled. Byte enables are active
high.
1 You cannot use the byte enable feature when using the error correction coding (ECC)
feature on M144K blocks.
Figure 3–1 shows how the write enable (wren) and byte enable (byteena) signals
control the operations of the M9K and M144K memory blocks.
When a byte-enable bit is deasserted during a write cycle, the corresponding data byte
output can appear as either a “don’t care” value or the current data at that location.
The output value for the masked byte is controllable using the Quartus II software.
When a byte-enable bit is asserted during a write cycle, the corresponding data byte
output also depends on the setting chosen in the Quartus II software.
Figure 3–1. Byte Enable Functional Waveform for M9K and M144K
inclock
wren
address
an
a0
a1
a2
a0
a1
a2
data
XXXX
ABCD
XXXX
byteena
XX
10
01
11
XX
contents at a0
FFFF
ABFF
contents at a1
FFFF
FFCD
contents at a2
don't care: q (asynch)
current data: q (asynch)
FFFF
doutn
doutn
ABXX
ABFF
XXCD
FFCD
ABCD
ABCD
ABCD
ABFF
ABFF
FFCD
FFCD
ABCD
ABCD
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation