EP2AGX95EF29C6N Datasheet, PDF (255/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
8–9
Differential Transmitter
Figure 8–5. Serializer Bypass Path (Note 1), (2), (3)
tx_in ₁₀
FPGA
Fabric
Serializer 2
DIN DOUT
tx_coreclock
3
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
PLL (4)
IOE supports SDR, DDR, or
IOE
Non-Registered Datapath
tx_out
+
-
LVDS Transmitter
tx_inclock
LVDS Clock Domain
Notes to Figure 8–5:
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, tx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width to the IOE is 1 and 2 bits, respectively.
(4) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
Differential applications often require specific clock-to-data alignments or a specific
data rate to clock rate factors. You can configure any Arria II LVDS transmitter to
generate a source-synchronous transmitter clock output. This flexibility allows the
placement of the output clock near the data outputs to simplify board layout and
reduce clock-to-data skew. The output clock can also be divided by a factor of 1, 2, 4, 6,
8, or 10, depending on the serialization factor. The phase of the clock in relation to the
data can be set at 0° or 180° (edge or center aligned). The PLLs provide additional
support for other phase shifts in 45° increments. These settings are made statically in
the Quartus^® II MegaWizard^™ Plug-In Manager software.
Figure 8–6 shows the Arria II LVDS transmitter in clock output mode. In clock output
mode, you can use an LVDS data channel as a clock output channel.
Figure 8–6. LVDS Transmitter in Clock Output Mode
Transmitter Circuit
Parallel
Series
FPGA
Fabric
txclkout+
txclkout–
PLL
diffioclk
(1)
LVDS_LOAD_EN
Note to Figure 8–6:
(1) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration