EP2AGX95EF29C6N Datasheet, PDF (45/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Adaptive Logic Modules
2–15
LUT-Register Mode
LUT-Register mode allows third register capability in an ALM. Two internal feedback
loops allow combinational ALUT1 to implement the master latch and combinational
ALUT0 to implement the slave latch needed for the third register. The LUT register
shares its clock, clock enable, and asynchronous clear sources with the top dedicated
register. Figure 2–12 shows the register constructed using two combinational blocks in
the ALM.
Figure 2–12. LUT Register from Two Combinational Blocks
sumout
clk
LUT regout
4-input
combout
aclr
LUT
Master latch
datain(datac)
sclr
5-input
LUT
sumout
combout
Slave latch
Figure 2–13 shows the ALM in LUT-Register mode.
Figure 2–13. ALM in LUT-Register Mode with 3-Register Capability
clk [2..0] aclr [1..0]
reg_chain_in
DC1
E0
F1
Third register
datain
aclr
sclr regout
latchout
aclr
datain
sdata _regout
lelocal 0
leout 0 a
leout 0 b
aclr
datain
lelocal 1
E1
F0
sdata _regout
leout 1 a
leout 1 b
reg_chain_out
December 2010 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration