EP2AGX95EF29C6N Datasheet, PDF (230/380 Pages) Altera Corporation – Device Interfaces and Integration

7–28
Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
For Arria II GZ devices, each bank can use settings from either or both adjacent DLLs
the bank. For example, DQS1L can get its phase-shift settings from DLL0, while DQS2L
can get its phase-shift settings from DLL1.
1 If you have a dedicated PLL that only generates the DLL input reference clock, set the
PLL mode to No Compensation or the Quartus II software automatically changes it.
Because the PLL does not use any other outputs, it does not have to compensate for
any clock paths.
1 Arria II devices support PLL cascading. If you cascade PLLs, you must use PLLs
adjacent to each other (for example, PLL5 and PLL6 for Arria II GX devices) so that
the dedicated path between the two PLLs is used instead of using a global clock
(GCLK) or regional clock (RCLK) network that might be subjected to core noise. The
TimeQuest Timing Analyzer takes PLL cascading into consideration for timing
analysis.
Table 7–5 lists the DLL location and supported I/O banks for Arria II GZ devices.
Table 7–5. DLL Location and Supported I/O Banks for Arria II GZ Devices
DLL
Location
Accessible I/O Banks (1)
DLL0
Top-left corner
1A, 1B, 1C, 2A, 2B, 2C, 7A, 7B, 7C, 8A, 8B, 8C
DLL1
Bottom-left corner
1A, 1B, 1C, 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, 4C
DLL2
Bottom-right corner
3A, 3B, 3C, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C
DLL3
Top-right corner
5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 8C
Note to Table 7–5:
(1) The DLL can access these I/O banks if they are available for memory interfacing.
Table 7–6 lists the reference clock for each DLL might come from PLL output clocks or
dedicated clock input pins for Arria II GX devices.
Table 7–6. DLL Reference Clock Input for Arria II GX Devices (Note 1)
DLL
CLKIN
(Top/Bottom)
CLKIN
(Right)
PLL
DLL0
CLK12
CLK13
CLK14
CLK15
—
PLL1
DLL1
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
PLL3
Note to Table 7–6:
(1) CLK4 to CLK7 are located on the bottom side, CLK8 to CLK11 are located on the right side, and CLK12 to CLK15
are located on the top side of the device.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation