EP2AGX95EF29C6N Datasheet, PDF (267/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
PLLs
8–21
PLLs
Arria II GX devices contain up to six PLLs with up to four center and corner PLLs
located on the right side of the device. Use the center/corner PLL on the right side of
the device to generate parallel clocks (rx_outclock and tx_outclock) and high-speed
clocks (diffioclk) for the SERDES and DPA circuitry. Figure 8–1 on page 8–3 shows
the locations of the PLLs for Arria II GX devices. Clock switchover and dynamic
reconfiguration are allowed using the center/corner PLLs in high-speed differential
I/O support mode.
Arria II GZ devices contain up to four left and right PLLs with up to two PLLs located
on the left side and two on the right side of the device. The left PLLs can support
high-speed differential I/O banks on the left side; the right PLLs can support
high-speed differential I/O banks on the right side of the device. The high-speed
differential I/O receiver and transmitter channels use these left and right PLLs to
generate the parallel clocks (rx_outclock and tx_outclock) and high-speed clocks
(diffioclk). Figure 8–2 on page 8–4 shows the locations of the left and right PLLs for
Arria II GZ devices. The PLL VCO operates at the clock frequency of the data rate.
Clock switchover and dynamic reconfiguration are allowed using the left and right
PLL in high-speed differential I/O support mode.
f For more information about PLLs, refer to the Clock Network and PLLs in Arria II
Devices chapter.
LVDS and DPA Clock Networks
Arria II GX devices only have LVDS and DPA clock networks on the right side of the
device. The center/corner PLLs feed into the differential transmitter and receiver
channels through the LVDS and DPA clock networks. Figure 8–17 and Figure 8–18
show the LVDS clock tree for family members without center PLLs and with center
PLLs, respectively. The center PLLs can drive the LVDS clock tree above and below
them. In Arria II GX devices with or without center PLLs, the corner PLLs can drive
both top and bottom LVDS clock tree.
Figure 8–17. LVDS and DPA Clock Networks in the Arria II GX Devices without Center PLLs
Quadrant
No LVDS and DPA
clock networks on the
left side of the device
Quadrant
Quadrant
Quadrant
Corner ⁴
PLL
4
DPA
Clock
LVDS
Clock
8
4
Corner ₄
PLL
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration