EP2AGX95EF29C6N Datasheet, PDF (70/380 Pages) Altera Corporation – Device Interfaces and Integration

3–22
Chapter 3: Memory Blocks in Arria II Devices
Design Considerations
Figure 3–21 shows sample functional waveforms of same-port read-during-write
behavior in new data mode.
Figure 3–21. M9K and M144K Blocks Same Port Read-During Write: New Data Mode
clk_a
address
rdena
wrena
byteena
data_a
q_a (asynch)
0A
0B
01
10
00
11
A123
B456
C789 DDDD
EEEE FFFF
XX23
B4XX XXXX DDDD EEEE FFFF
Figure 3–22 shows sample functional waveforms of same-port read-during-write
behavior in old data mode.
Figure 3–22. M9K and M144K Blocks Same Port Read-During-Write: Old Data Mode
clk_a
address
rdena
wrena
byteena
data_a
q_a (asynch)
A0
A1
01
10
00
11
A123
B456
C789 DDDD
EEEE FFFF
A0 (old data) D_oldD_old23 B423 A1(old data) DDDD
EEEE
For MLABs, the output of the MLABs can only be set to don’t care in same-port
read-during-write mode. In this mode, the output of the MLABs is unknown during a
write cycle. There is a window near the falling edge of the clock during which the
output is unknown. Prior to that window, “old data” is read out; after that window,
“new data” is seen at the output.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation