EP2AGX95EF29C6N Datasheet, PDF (204/380 Pages) Altera Corporation – Device Interfaces and Integration

7–2
Chapter 7: External Memory Interfaces in Arria II Devices
Figure 7–1 and Figure 7–2 show the memory interface datapath overview for
Arria II GX and Arria II GZ devices, respectively.
Figure 7–1. External Memory Interface Datapath Overview for Arria II GX Devices (Note 1) , (2)
Arria II GX FPGA
DLL
DQS Logic
Block
Postamble Enable
Postamble Clock
Postamble
Control
Circuit
2n
Internal Memory
(3)
Synchronization
Registers
DQS Enable
Circuit
2n
DDR Input
Registers
Memory
DQS (Read) (4)
n
DQ (Read) (4)
Clock
Management
and Reset
Resynchronization Clock
DQ Write Clock
DQS Write Clock
2n
DDR Output
and Output
Enable
Registers
2
DDR Output
and Output
Enable
Registers
n
DQ (Write) (4)
DQS (Write) (4)
Notes to Figure 7–1:
(1) You can bypass each register block.
(2) Shaded blocks are implemented in the I/O element (IOE).
(3) The memory blocks used for each memory interface may differ slightly.
(4) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read
and write operations.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation